Webinar disclaimer

This webinar is a dissemination activity of the INPROVOL project funded by Vlaio.

Plated through hole via failures: is this a risk for my design?


In cEDM’s ‘reliability FMEA’ tool, we listed about 15 different failure mechanisms which over time can lead to electrical malfunctioning of the Printed Circuit Board (PCB) itself. One of the most dominant failures which are purely related to the PCB, is fracturing of the copper plated through hole via’s. These are induced by the thermal expansion mismatch between the plated copper via and the surrounding epoxy/glass material. Due to this CTE mismatch, the copper is stressed during solder reflow cycles and during operational temperature cycling. Both multiple solder reflows and numerous temperature cycles can lead to cracked via’s.

In this webinar, we will explain the basics of this PTH via failure mechanism, what are the design and material parameters accelerating this failure and how the life time of your particular PCB with 100-1000 via’s can be calculated. This latter one is needed to finally guarantee that PTH via failures will not occur during the required life time of the PCB.

Presented by: Bart Vandevelde (imec)

Wednesday, November 8, 2017 - 10:00
Participation fee: 

Free of charge, but registration is required.